In the mobile communication system, the data transferred in the channel will generate some redundant data after the channel coding, and the redundant information is used to provide more decoding information for the decoder to improve the success ratio of decoding, however a decreasing of transfer efficiency will be caused if all of the redundant information is transferred. Therefore, at present, a preferred method is to select the amount of the transfer information according to the quality of the channel, for example only the original information is transferred when the channel quality is better, whereas more check bits are transferred with the original information bits when the channel quality is not that good. That is, it is needed to select the transferred data generated by the channel coder to transfer, and the rate matching is to implement the function of selecting the transferred coding data.
Nowadays, a method for matching rates—cyclic buffer rate matching, that is totally different from the R6, is adopted in the Long Term Evolution (LTE) system. The advantage of the algorithm is that the repeating and puncturing can be implemented conveniently, that is, the implementation of the rate matching at any data rate is very simple, wherein the main ways for implementing the rate matching include software implementation ways and hardware implementation ways. Since the amount of the data traffic in the LTE system is very large, the time maintained for processing the rate matching is very short, and if the way of software implementation is used, the requirements for the processor are very high, and the costs therewith are increased dramatically. If hardware processing is performed according to the steps described in the protocol, the coded data are interleaved and stored in three storages and then are tailored, especially, interleaved-reading is required when processing the data in the check 1 storage and check 2 storage, which is very complicated and a lot of power consumption will be produces during the constant conversion process of the address.
Therefore, further improvements are made to the existing implementation technology.
For example, the existing rate matching includes operations of intra-block interleaving, and collection, selection, and transmission of bits and so on, the principle of which is shown in FIG. 1, wherein the input data streams dk(0), dk(1) and dk(2) respectively correspond to the system bit S, the first parity check bit P1 (or may be called check 1 briefly) and the second parity check bit P2 (or may be called check 2) output by the Turbo coder. According to the flow direction shown in FIG. 1, the interleaving processing has been performed on the system bit, check 1 and check 2 respectively at first, while the intra-block interleaving processed vk(0), vk(1) and vk(2) are collected into the virtual buffer sequence wk in accordance with specified rules, wherein the data in the virtual buffer is read according to the initial position and the size of the soft buffer (NCB), wherein the data in the system bit buffer are read in sequence, and the data in the check bit buffer are read in an interleaved way, and it is judged whether the read data are valid data, and if the read data are invalid data, the read data are neglect and it is continued to read, or else, the valid data are output.
The existing rate matching process is described in detail as follows, wherein the numbers of row and column interleavers and indexes of various data are all numbered from 0, and the input three data streams dk(0), dk(1) and dk(2) have equal length. It is assumed that the lengths of the three data streams are D, and then the input data sequence is d0(i), d1(i), d2(i), . . . , dD-1(i), wherein i equals to 0, 1, and 2, which respectively correspond to the system bit S, check bit P1 and check bit P2.
Step 1: The Number of Required Rows and the Number of Dummy Bits are Calculated.
Since the number of columns C of the intra-block interleaver is set to 32 invariably, the number of rows R of the intra-block interleaver is
  R  =            ⌈              D        C            ⌉        .  
When R×C>D, extra dummy bits require padding, and the number of dummy bits ND is:ND=(R×C−D).
Step 2: The Dummy Bits and Data Streams are Written.
The dummy bits are written into the interleaver by rows at first, and then the data stream dk(i) is written into the interleaver by rows, and an R×C matrix is constituted as follows:
      [                                        y            0                                                y            1                                                y            2                                    …                                      y                          C              -              1                                                                        y            C                                                y                          C              +              1                                                            y                          C              +              2                                                …                                      y                                          2                ⁢                C                            -              1                                                            ⋮                          ⋮                          ⋮                          ⋱                          ⋮                                                  y                                          (                                  R                  -                  1                                )                            ×              C                                                            y                                                            (                                      R                    -                    1                                    )                                ×                C                            +              1                                                            y                                                            (                                      R                    -                    1                                    )                                ×                C                            +              2                                                …                                      y                          (                                                R                  ×                  C                                -                1                            )                                            ]    wherein            y      k        =          {                                                  〈              NULL              〉                                                          k              <                              N                D                                                                                        d                              k                -                                  N                  D                                            i                                                          k              ≥                              N                D                                                        
Step 3: Column Transposition is Performed and Data are Read.
The LTE adopts interleavers with different parameters for different data streams, which is described respectively below.
Sub-Interleaver 1
The column numbers of the R×C matrix are 0, . . . , C−1. Column transposition is performed on P(j)jε{0, 1, . . . , C−1} according to the transposition pattern shown in FIG. 1, that is, P(j) is the column number of the jth column before the transposition.
TABLE 1 is an inter-column interleaving pattern table
Column transposition pattern <P(0), P(1), . . . , P(C − 1)><0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14,30, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11, 27, 7, 23,15, 31>
The matrix after the column transposition is as follows:
         [                                        y                          P              ⁡                              (                0                )                                                                          y                          P              ⁡                              (                1                )                                                                          y                          P              ⁡                              (                2                )                                                              …                                      y                          P              ⁡                              (                                  C                  -                  1                                )                                                                                      y                                          P                ⁡                                  (                  0                  )                                            +              C                                                            y                                          P                ⁡                                  (                  1                  )                                            +              C                                                            y                                          P                ⁡                                  (                  2                  )                                            +              C                                                …                                      y                                          P                ⁡                                  (                                      C                    -                    1                                    )                                            +              C                                                            ⋮                          ⋮                          ⋮                          ⋱                          ⋮                                                  y                                          P                ⁢                                  (                  0                  )                                            +                                                (                                      R                    -                    1                                    )                                ×                C                                                                          y                                          P                ⁡                                  (                  1                  )                                            +                                                (                                      R                    -                    1                                    )                                ×                C                                                                          y                                          P                ⁡                                  (                  2                  )                                            +                                                (                                      R                    -                    1                                    )                                ×                C                                                              …                                      y                                          P                ⁡                                  (                                      C                    -                    1                                    )                                            +                                                (                                      R                    -                    1                                    )                                ×                C                                                          ]  
The above matrix is output by columns to obtain an output sequence v0(i), v1(i), v2(i), . . . , vKΠ−1, wherein v0(i) corresponds to yP(0), v1(i) corresponds to yP(0)+C, and KΠ=(R×C).
Sub-Interleaver 2
The existing sub-interleaver 2 is a result of 1 bit offset of sub-interleaver 1. Therefore, it is easy to obtain from the above analysis that the corresponding relationship between the output and the input of sub-interleaver 2 is:
      π    ⁡          (      k      )        =            (                        P          ⁡                      (                          ⌊                              k                R                            ⌋                        )                          +                  C          ×                      (                          k              ⁢                                                          ⁢              mod              ⁢                                                          ⁢              R                        )                          +        1            )        ⁢    mod    ⁢                  ⁢          K      Π      
Step 4: Bits Collection.
A cyclic buffer with a size of 3KΠ is defined, and then the three data on which the interleaving processing is performed are collected as a following method.
      w    k    ⁢      {                                        v            k                          (              0              )                                                                          k              =              0                        ,            1            ,            …            ⁢                                                  ,                                          K                Π                            -              1                                                                        v                                          (                                  k                  -                                      K                    Π                                                  )                            /              2                                      (              1              )                                                                          k              =                              K                Π                                      ,                                          K                Π                            +              2                        ,            …            ⁢                                                  ,                                          3                ×                                  K                  Π                                            -              2                                                                        v                                          (                                  k                  -                                      K                    Π                                    -                  1                                )                            /              2                                      (              2              )                                                                          k              =                                                K                  Π                                +                1                                      ,                                          K                Π                            +              3                        ,            …            ⁢                                                  ,                                          3                ×                                  K                  Π                                            -              1                                          
Step 5: The Length of the Bit Sequence Output after the Rate Matching is Calculated.
Four parameters are needed in the calculation in this step, which are respectively:
1) G—the sum of the number of bits of all of the code blocks output after the rate matching, that is, the number of bits that a transport block is able to transfer;
2) M—modulation ways, which is QPSK, 16 QAM or 64 QAM;
3) C—the number of code blocks;
4) r—the index of the present code block, the numbers of which are 0, . . . C−1.
The calculation of the length of the sequence output after the rate matching is as follows:
      Q    m    =      {                            2                                                    for              ⁢                                                          ⁢              M                        =            QPSK                                                4                                                    for              ⁢                                                          ⁢              M                        =                          16              ⁢              QAM                                                            6                                                    for              ⁢                                                          ⁢              M                        =                          64              ⁢              QAM                                          G′=G/Qm 
Let γ=G′ mod C, and the calculation of E is as follows:if r≦C−γ−1E=Qm·└G′/C┘; elseE=Qm·┌G′/C┐; end
Step 6: The Selection and Deletion of Data.
The initial position k0=R×(24×RVidx+2).
Let k=0, j=0while (k<E)if w(k0+j)mod Kw≠<NULL>ek=w(k0j)mod Kw;k=k+1;endj=j+1;                end        
wherein Kw=3×KΠ, and <NULL> is common term for the padding bits added during dividing the code block and the dummy bits added during the interleaving of the code block.
The existing implementation schemes are all based on the description in TS36.212: first interleaved-storing the system bit, check 1 and check 2 in three storages, and then reading data from the system bit storage according the parameter configuration, or interleaved-reading data from check 1 and check 2 storages, and then tailoring the data.
It can be seen from above that three storages are needed in the related art, and it is needed to distinguish whether the data to be stored are system bit data or check 1 data or check 2 data in the storing process. Besides, in the related art, the boundary of the storage needs to be judged at each time, and the address multiplexing is needed, and therefore, the system is complex with large power consumption.